import chisel3.RawModule
import halftone.errdiff.ErrDiffCorePip
import halftone.errdiff.pipeline.{ErrorInPip, ErrorOutPip, PixelGetPip, ThreshCalcPip, WriteBinaryPip}
import halftone.{ErrDiffConfig, ErrDiffCoreWrapper}
import halftone.errdiff.ErrDiffCoreSeq

object EmittedModule {
  // Chisel Module needs to be created in a certain `builder context`
  // So the function object format is necessary
  // Rather than just Class instantiation
  def ExposedModules: List[() => RawModule] = List(
//    () => new MemAccessByAXI,
//    () => new AXI4MasterModule(32, 32),
//    () => new AXI4SlaveModule(32, 32),
//    () => new ErrDiffCoreSeq(ErrDiffConfig()),
    () => new ErrDiffCoreWrapper(ErrDiffConfig())
  )
}
